Fabrication approach for lateral InGaAs tunnel transistors

In this work, the lateral InGaAs tunnel FET is configured and sized to enable gate control of the Zener (reverse bias) tunneling current. The p+InGaAs transistor channel is 4 nm thick with a n+p+ source injector and a thin 3/3 nm HfO 2 /Al 2 O 3 high-k gate dielectric. Atomic-layer deposition (ALD)...

Full description

Saved in:
Bibliographic Details
Published in2009 International Semiconductor Device Research Symposium pp. 1 - 2
Main Authors Wheeler, D., Kabeer, S., Yeqing Lu, Vasen, T., Qin Zhang, Guangle Zhou, Clark, K., Haijun Zhu, Yung-Chung Kao, Fay, P., Kosel, T., Huili Xing, Seabaugh, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2009
Subjects
Aluminum oxide
Fabrication
FETs
Hafnium oxide
Indium gallium arsenide
Indium phosphide
Molecular beam epitaxial growth
Plasma temperature
Substrates
Wet etching
Online AccessGet full text

Cover

More Information
Summary:In this work, the lateral InGaAs tunnel FET is configured and sized to enable gate control of the Zener (reverse bias) tunneling current. The p+InGaAs transistor channel is 4 nm thick with a n+p+ source injector and a thin 3/3 nm HfO 2 /Al 2 O 3 high-k gate dielectric. Atomic-layer deposition (ALD) is used to deposit the gate dielectric.
ISBN:1424460301
9781424460304
DOI:10.1109/ISDRS.2009.5378160