A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS

• Published in: 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers pp. 542 - 634
• Main Authors: Zhiheng Cao, Shouli Yan, Yunchu Li
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2008
• Subjects: Calibration; Capacitors; Clocks; CMOS logic circuits; CMOS process; Delay; Energy consumption; Frequency; Magnetic recording; Sampling methods
• ISBN: 1424420105; 9781424420100
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2008.4523297

ADCs with 6b resolution and gigahertz sampling frequency are widely used in serial links, magnetic recording systems and UWB receivers. Flash ADCs have been dominantly used for these applications. This paper presents an ADC that takes advantage of the high-speed digital logic and highly matched small capacitors in deep-submicron digital CMOS processes to achieve similar performance, but with lower power consumption than flash ADCs. Unlike many previously published low-power high-speed ADCs based on time-interleaved SAR, this ADC has only 2 clock-cycle latency (1.6ns at 1.25GS/s) and achieves 6b performance without any digital post-processing or off-line calibration, making it a plug- in replacement for conventional flash ADCs in many applications.