Exploiting Dynamic Reconfiguration for FPGA Based Network Intrusion Detection Systems

• Published in: 2010 International Conference on Field Programmable Logic and Applications pp. 10 - 14
• Main Authors: Pontarelli, S, Greco, C, Nobile, E, Teofili, S, Bianchi, G
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2010
• Subjects: Engines; Field programmable gate arrays; Hardware; Inspection; Protocols; Queueing analysis; Software
• ISBN: 9781424478422; 1424478421
• ISSN: 1946-147X
• DOI: 10.1109/FPL.2010.13

A Network Intrusion Detection System (NIDS) inspects the traffic flowing in a network to detect malicious content such as spam, viruses, and so on. Hardware based solutions appear necessary to face the performance requirements emerging when the goal is to deploy such systems in high speed network scenarios. However, the appropriate choice of the hardware platform is believed to be subject to at least two requirements, usually considered independent each other: i) it needs to be reprogrammable, in order to update the intrusion detection rules each time a new threat arises, and ii) it must be capable of containing the typically very large set of rules of existing NIDSs. The goal of this paper is to show that reprogrammability can be further exploited to reduce the resource requirements for the chosen platform. Specifically, we propose an FPGA-based solution that classifies and dispatches traffic to elastic buffers, connecting one buffer at a time to a dynamically reconfigurable rule matching core. This core supports only the appropriate subset of detection rules. A worst-case analysis shows that the saving in hardware resources is achieved with a relatively small buffer space, currently available in cheap, low end, FPGA boards, with no impairment on the resulting throughput.