Pushing the scaling limits of embedded non-volatile memories with high-K materials

In this paper, two alternative cell concepts to overcome these issues were discussed: conventional floating gate cells with high-K inter-poly dielectrics (IPD) and nitride trapping devices with high-K materials. In both concepts, the reduced equivalent oxide thickness (EOT) of the high-K layers help...

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Bibliographic Details
Published in2006 IEEE International Conference on IC Design and Technology pp. 1 - 4
Main Authors van Duuren, M., van Schaijk, R., Slotboom, M., Tello, P.G., Akil, N., Miranda, A.H., Golubovic, D.S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2006
Subjects
Character generation
Flash memory
Hafnium oxide
High K dielectric materials
High-K gate dielectrics
Leakage current
Nonvolatile memory
SONOS devices
Tunneling
Voltage
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Summary:In this paper, two alternative cell concepts to overcome these issues were discussed: conventional floating gate cells with high-K inter-poly dielectrics (IPD) and nitride trapping devices with high-K materials. In both concepts, the reduced equivalent oxide thickness (EOT) of the high-K layers helps reducing VPE, whereas the low leakage current ensures a good data retention. In this work, only hafnium based high-K materials were used: hafnium oxide (HfO 2 ) and nitrided hafnium silicate (HfSiON), both deposited by MOCVD. The choice for these materials was based on their expected availability in the sub-45nm CMOS nodes
ISBN:142440097X
9781424400973
ISSN:2381-3555
2691-0462
DOI:10.1109/ICICDT.2006.220786