Vertical Structure NAND flash array integration with paired FinFET multi-bit scheme for high-density NAND flash memory application

Multi-bit vertical structure NAND (VsNAND) flash memories with 32-paired FinFET cell string have been successfully integrated for the first time. Its array integration issues regarding the sub-10 nm vertical structure fin could be solved by proper choices of isolation material, ion implantation, and...

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Published in2008 Symposium on VLSI Technology pp. 120 - 121
Main Authors June-Mo Koo, Tae-Eung Yoon, Taehee Lee, Sungjae Byun, Young-Gu Jin, Wonjoo Kim, Sukpil Kim, Jongbong Park, Junseok Cho, Jeong-Dong Choe, Choong-Ho Lee, Jong Jin Lee, Je-Woo Han, Yunseung Kang, Sangjun Park, Byoungho Kwon, Yong-Ju Jung, Inkyoung Yoo, Yoondong Park
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2008
Subjects
Arrays
Computer architecture
FinFETs
Flash memory
Logic gates
Periodic structures
Silicon compounds
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Summary:Multi-bit vertical structure NAND (VsNAND) flash memories with 32-paired FinFET cell string have been successfully integrated for the first time. Its array integration issues regarding the sub-10 nm vertical structure fin could be solved by proper choices of isolation material, ion implantation, and word line patterning. VsNAND flash array cells with TANOS (TaN/Al 2 O 3 /SiN/SiO x /Si) charge trap structure show possibilities of acceptable program/erase properties and cell Vth distribution characteristics for multi-level NAND flash application.
ISBN:142441802X
9781424418022
ISSN:0743-1562
DOI:10.1109/VLSIT.2008.4588586