Solder paste optimization in thermal pad padstack

In this paper is presented an important solder paste optimization for thermal pads used for Quad Flat No leads (QFNs) and Small Outline No leads (SONs) packages. The PCB (printed circuit board) must be designed to have an excellent heat conductivity for them, incorporating a thermal pad and thermal...

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Bibliographic Details
Published in2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME) pp. 125 - 128
Main Authors Damian, I., Branescu, C., Soare, V.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2012
Subjects
Electronic packaging thermal management
Electronics packaging
Fabrication
Graphics
Lead
Mentor Graphics
PCB
Printed circuits
solder paste pad
Thermal pad
Transmission line matrix methods
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Summary:In this paper is presented an important solder paste optimization for thermal pads used for Quad Flat No leads (QFNs) and Small Outline No leads (SONs) packages. The PCB (printed circuit board) must be designed to have an excellent heat conductivity for them, incorporating a thermal pad and thermal vias on it. This can be achieved by creating a special padstack for thermal pad, with a complex solder paste, created in a matrix of squares leaving channels for thermal vias. This way, the quantity of solder paste used in fabrication process is smaller than the case of a full filled solder paste pad, avoiding solder leakage through vias. The novelty of the paper is represented by creating a complex solder paste pad, using a template, like a starting point for the rest of thermal pads included in Mentor Graphics Expedition software library.
ISBN:1467347604
9781467347600
DOI:10.1109/SIITME.2012.6384360