A Motion Estimation IP with Low Memory Access for H.264/AVC Encoder Based on Fully Parallel Hardware-Oriented Algorithm

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip...

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Bibliographic Details
Published in2010 Proceedings of 19th International Conference on Computer Communications and Networks pp. 1 - 4
Main Authors Shi Hye Kim, Nam Thang Ta, Jeong Hoon Kim, Jun Rim Choi
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2010
Subjects
Algorithm design and analysis
Automatic voltage control
Computer architecture
Motion estimation
Software
Software algorithms
Throughput
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Summary:In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The synthesis results show that the IP core occupies 907K logic gates and achieves high throughput supporting HDTV 720p 30 fps.
ISBN:9781424471140
1424471141
ISSN:1095-2055
2637-9430
DOI:10.1109/ICCCN.2010.5560051