Scalability with silicon nitride encapsulation layer for Ti/HfOx pillar RRAM

In this work, the nanoscale Ti/HfO 2 based resistive memory with pillar structure was fabricated. The architecture of the pillar device shows the advantages of reduced parasitic capacitance effect and simple process flow. The effects of the passivated layer on the nanoscale RRAM are also studied. Re...

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Bibliographic Details
Published inProceedings of 2010 International Symposium on VLSI Technology, System and Application pp. 146 - 147
Main Authors Pei-Yi Gu, Yu-Sheng Chen, Heng-Yuan Lee, Pang-Shiu Chen, Wen-Hsing Liu, Wei-Su Chen, Yen-Ya Hsu, Chen, Frederick, Ming-Jinn Tsai
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2010
Subjects
Atomic layer deposition
Degradation
Encapsulation
Hafnium oxide
Nanoscale devices
Parasitic capacitance
Scalability
Silicon
Temperature
Tin
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Summary:In this work, the nanoscale Ti/HfO 2 based resistive memory with pillar structure was fabricated. The architecture of the pillar device shows the advantages of reduced parasitic capacitance effect and simple process flow. The effects of the passivated layer on the nanoscale RRAM are also studied. Reduction of the interaction between the memory device and the encapsulating layer plays an important role for the enlarging resistive switching window of the nanoscale RRAM. Finally, a nanoscale Ti/HfO 2 resistive memory with improved memory performance through an appropriate passivation layer was demonstrated.
ISBN:9781424450633
1424450632
ISSN:1524-766X
2690-8174
DOI:10.1109/VTSA.2010.5488909