A high-performance triple patterning layout decomposer with balanced density

Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high performance layout decomposer for TPL. Density balancing is seamlessly integrated into all key steps in our TPL layout decompo...

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Bibliographic Details
Published in2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) pp. 163 - 169
Main Authors Bei Yu, Yen-Hung Lin, Luk-Pat, Gerard, Duo Ding, Lucas, Kevin, Pan, David Z.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2013
Subjects
Color
Layout
Lithography
Partitioning algorithms
Programming
Runtime
Vectors
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Summary:Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high performance layout decomposer for TPL. Density balancing is seamlessly integrated into all key steps in our TPL layout decomposition, including density-balanced semi-definite programming (SDP), density-based mapping, and density-balanced graph simplification. Our new TPL decomposer can obtain high performance even compared to previous state-of-the-art layout decomposers which are not balanced-density aware, e.g., by Yu et al. (ICCAD'11), Fang et al. (DAC'12), and Kuang et al. (DAC'13). Furthermore, the balanced-density version of our decomposer can provide more balanced density which leads to less edge placement error (EPE), while the conflict and stitch numbers are still very comparable to our non-balanced-density baseline.
ISSN:1092-3152
1558-2434
DOI:10.1109/ICCAD.2013.6691114