A time-interleaved multi-mode ΔΣ RF-DAC for direct digital-to-RF synthesis

• Published in: 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) pp. 103 - 106
• Main Authors: McCue, Jamin J., Dupaix, Brian, Duncan, Lucas, Patel, Vipul J., Quach, Tony, Khalil, Waleed
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2015
• Subjects: Bandwidth; Baseband; Clocks; delta sigma modulation; Frequency modulation; high-pass modulation; I/Q; image rejection; interleaving; Radio frequency; RF-DAC; Silicon germanium
• DOI: 10.1109/RFIC.2015.7337715

A multi-mode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. Unlike embedded-mixer ΔΣ RF-DACs which require analog I/Q combining and precise alignment of the local oscillator (LO) and data clock, the proposed circuit is fully digital with only one clock frequency (f S ). This architecture eliminates the need for a widely-tuned LO by reconfiguring the ΔΣ modulator (DSM) for a variety of output frequencies, thus making it suitable for software-defined radio. Both a band-pass (BP) and high-pass (HP) DSM are used to synthesize signals at f S /4, f S /2, or 3f S /4. Interleaving is used to reject the first DAC image, doubling the usable bandwidth of the HP DSM while reducing reconstruction filter requirements. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS. With an f S of 2 GHz, the 0.18 mm 2 RF-DAC core consumes 55 mW with output powers of -4.5 dBm, -7.5 dBm, and -13.8 dBm at 0.5 GHz, 1 GHz, and 1.5 GHz, respectively. For the HP DSM, a signal-to-image rejection ratio (SIRR) of 72 dB, an SNR of 54.5 dB over a 50 MHz bandwidth, and an in-band SFDR of 58.5 dB are demonstrated.