Performance of Graceful Degradation for Cache Faults

• Published in: IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) pp. 409 - 415
• Main Authors: Hyunjin Lee, Sangyeun Cho, Childers, B.R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2007
• Subjects: Aging; Circuit faults; CMOS technology; Degradation; Hardware; Manufacturing processes; Microarchitecture; Microprocessors; Redundancy; Testing
• ISBN: 0769528961; 9780769528960
• ISSN: 2159-3469; 2159-3477
• DOI: 10.1109/ISVLSI.2007.81

In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchitectural techniques to make processor components resilient to hard faults become increasingly important. This paper considers defects in cache memory and studies their impact on program performance using a fault degradable cache model. We first describe how defects at the circuit level in cache manifest themselves at the microarchitecture level. We then examine several strategies for masking faults, by disabling faulty resources, such as lines, sets, ways, ports, or even the whole cache. We also propose an efficient cache set remapping scheme to recover lost performance due to failed sets. Using a new simulation tool, called CAFE, we study how the cache faults impact program performance under the various masking schemes