Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack

Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to pla...

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Published in2006 International Electron Devices Meeting pp. 1 - 4
Main Authors Ernst, T., Dupre, C., Isheden, C., Bernard, E., Ritzenthaler, R., Maffini-Alvaro, V., Barbe, J.C., De Crecy, F., Toffoli, A., Vizioz, C., Borel, S., Andrieu, F., Delaye, V., Lafond, D., Rabille, G., Hartmann, J.M., Rivoire, M., Guillaumot, B., Suhm, A., Rivallin, P., Faynot, O., Ghibaudo, G., Deleonibus, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2006
Subjects
Charge carrier processes
CMOS process
Current density
Electron beams
Electron mobility
FinFETs
Hafnium oxide
Time measurement
Tin
Transmission line matrix methods
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Summary:Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2 /TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO 2 /TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed
ISBN:142440438X
9781424404384
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2006.346955