A 2nd-order Delta Sigma AD modulator using dynamic amplifier and dynamic SAR quantizer

A proof-of-concept Delta Sigma AD modulator using dynamic analog components is designed and fabricated in 90nm CMOS technology. The measurement results of an experimental prototype demonstrate the feasibility of the proposed switched-capacitor (SC) architecture to realize a 2nd-order Delta Sigma AD...

Full description

Saved in:
Bibliographic Details
Published in2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) pp. 1 - 5
Main Authors Chunihui Pan, Hao San, Shibata, Tsugumichi
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2016
Subjects
Adders
Capacitors
CMOS technology
Dynamic comparator
Feedforward neural networks
Modulation
Multi-bit Delta Sigma modulator
Power demand
Prototypes
Ring amplifier
Online AccessGet full text

Cover

More Information
Summary:A proof-of-concept Delta Sigma AD modulator using dynamic analog components is designed and fabricated in 90nm CMOS technology. The measurement results of an experimental prototype demonstrate the feasibility of the proposed switched-capacitor (SC) architecture to realize a 2nd-order Delta Sigma AD modulator with ring amplifier based integrators and dynamic comparator based successive approximation register (SAR) quantizer. The integrators in the modulator are realized by ring amplifier without static current. Multi-bit quantizer and analog adder in the feedforward modulator is realized by a passive-adder embedded SAR analog-to-digital converter (ADC) which consists of capacitor array and a dynamic comparator. The dynamic comparator does not dissipate static power when a pre-amplifier is not used. Measurement results of peak SNDR=77.51dB and SNR=80.08dB are achieved while a sinusoid -1dBFS input is sampled at 12MS/s for the bandwidth is BW=94kHz. The total analog power consumption of the modulator is 0.37mW while the supply voltage is 1.1V.
DOI:10.1109/ISPACS.2016.7824725