Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI

We present a design and characterization method for a scalable ultra-wide voltage range (UWVR) SRAM bitcell array, targeting a minimum voltage prediction, high yield and Si-CAD correlation within 5%. The experimental validation is first performed in bulk CMOS 65nm, then confirmed in 28nm FDSOI. Over...

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Published in2013 Proceedings of the ESSCIRC (ESSCIRC) pp. 205 - 208
Main Authors Abouzeid, Fady, Bienfait, Audrey, Akyel, Kaya Can, Clerc, Sylvain, Ciampolini, Lorenzo, Roche, Philippe
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2013
Subjects
Arrays
Low voltage
Microprocessors
Random access memory
Silicon
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Summary:We present a design and characterization method for a scalable ultra-wide voltage range (UWVR) SRAM bitcell array, targeting a minimum voltage prediction, high yield and Si-CAD correlation within 5%. The experimental validation is first performed in bulk CMOS 65nm, then confirmed in 28nm FDSOI. Over 10× energy gain is achieved from 1.2V down to 0.35V range while measuring high speed at nominal voltage.
ISBN:9781479906437
1479906433
ISSN:1930-8833
2643-1319
DOI:10.1109/ESSCIRC.2013.6649108