Rapid prototyping of a self-timed ALU with FPGAs

• Published in: 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) pp. 8 pp. - 7
• Main Authors: Ortega-Cisneros, S., Raygoza-Panduro, J.J., Suardiaz Muro, J., Boemo, E.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Arithmetic; Clocks; Delay; Design methodology; Displays; Field programmable gate arrays; Logic design; Microprocessors; Prototypes; Synchronization
• ISBN: 0769524567; 9780769524566
• ISSN: 2325-6532; 2640-0472
• DOI: 10.1109/RECONFIG.2005.33

This article presents the design and implementation of a self-timed arithmetic logic unit (ALU) that has been developed as part of an asynchronous microprocessor. This displays an inherent operational characteristic of low consumption, owing to the synchronization signals that stop when the execution of an operation finishes (stoppable clock); that is to say, the dynamic consumption is zero, while it is not required again by an external request signal. It demonstrates the methodology of design of the self-timed controls which synchronize the data transfer, as well as the characterization of delay macros designed in FPGA editor for the adjustment of ALU processing times. It also summarizes the results of the implementation for a FPGA Virtex II, as well as the parameters of area, distribution of tracks, delay, latency, consumption and fan-out.