Study of ground plane FD SOI structures at 25 nm

• Published in: International Conference on Nanoscience, Engineering and Technology (ICONSET 2011) pp. 187 - 189
• Main Authors: Singh, Avtar, Chatterjee, Arun Kumar
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2011
• Subjects: continuous ground plan; FD SOI; GPB; GPS; ground plane; Logic gates; MOSFET circuits; partial ground plane
• ISBN: 9781467300711; 1467300713
• DOI: 10.1109/ICONSET.2011.6167950

Silicon-On-Insulator (SOI) technology is a potential technology for future VLSI system implementations. SOI technology offers MOS devices with suppressed CMOS latch-up, higher packing density and higher speed. SOI MOSFET structures offer many advantages over conventional Bulk MOS transistor.In this paper, ground plane effect on FD SOI MOSFET has been discussed. There are two ways to insert the ground plane in FD SOI MOSFET structure, ground plane in substrate and ground plane in BOX. On the basis of ION/IOFF both structures are compared in this paper. GPB structure has high on current and off current ratio in comparison to GPS Structure. Further partial and continuous length ground plane are discussed and its effect on current driving capability and leakage current are studied. In last with the help of Subthreshold curve concluded that the leakage current is minimum in the GPB based structures. The work is carried out at 25 nm technology. The design & Simulations are done using ATLAS framework of SILVACO TCAD tool.