Low-power timing closure methodology for ultra-low voltage designs

• Published in: 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) pp. 697 - 704
• Main Authors: Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2013
• Subjects: Clocks; Delays; Power demand; Registers; Time factors; Wires
• ISSN: 1092-3152; 1558-2434
• DOI: 10.1109/ICCAD.2013.6691191

As the supply voltage is down to the ultra-low voltage (ULV) level, timing closure becomes a serious challenge in the use of multiple power modes. Due to a wide voltage range, a very huge clock skew may occur among different power modes. To reduce this huge clock skew, the conventional power-mode-aware clock tree often suffers from a huge overhead on power consumption. Moreover, at the ULV level, since the setup time and the hold time of each register dramatically increase, the number of timing violations also increases greatly. However, the existing minimum padding technique cannot fix hold time violations in multiple power modes. Based on those two observations, in this paper, we propose a low-power timing closure methodology, which incorporates the synthesis of clock tree and data path, for multipower-mode ULV designs. Our low-power timing closure methodology has two main approaches. First, we use multiple power modes to build a power-mode-aware clock tree for reducing clock skew with very small power consumption. Second, we propose the first multi-power-mode minimum padding technique to fix all the hold time violations in all the power modes simultaneously. Experimental results consistently show that the integration of both approaches yields the best results.