Deep submicron implementation of gating transistor power saving technique for power optimized code book SRAM

• Published in: 2009 4th IEEE Conference on Industrial Electronics and Applications pp. 2616 - 2619
• Main Authors: Mali, M., Sutaone, M.S., Bhalerao, M., Tak, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2009
• Subjects: CMOS technology; Code book; Educational institutions; Image coding; Logic; Mathematical model; Power dissipation; preharge; Random access memory; SPICE; SRAM; Vector Quantizers; Voltage
• ISBN: 9781424427994; 1424427991
• ISSN: 2156-2318; 2158-2297
• DOI: 10.1109/ICIEA.2009.5138681

Embedded SRAM has plentiful of applications in signal processing as an on chip RAM. The prime benefit is its speed compared to DRAM. The threat of dissipation is targeted here. This dissipation in code book SRAM in vector quantizers for image compression is reduced. The dissipation is measured at various combinations of supply voltage and precharge voltage of SRAM array. The optimized combination for minimum dissipation and speed is computed. These voltages are 620 mV and 300 mV for supply and precharge respectively. Additionally the power dissipation is also reduced by 7% to 13% by additional gating transistor and at different precharge levels. The access time is reduced to 2 ns. The reliability is improved by adding redundant rows and columns. The CMOS layout is done at 0.25 mum technology for an array size of 256times8 and 16 such arrays.