Direct fabrication of multi-tier structures in dielectric materials for dual damascene processing

• Published in: 2011 Semiconductor Conference Dresden pp. 1 - 5
• Main Authors: Jian He, Richter, K., Jahn, A., Bartha, J. W., Howitz, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2011
• Subjects: Dielectric materials; dual damascene; Fabrication; imprintable dielectric material; multi-tier template; Nanolithography; Polymers; Resists; Silicon; UV nanoimprint lithography
• ISBN: 1457704315; 9781457704314
• DOI: 10.1109/SCD.2011.6068757

In the back end of line (BEOL) processing of advanced microprocessors several levels (ten or more) of wiring and associated via (interconnects) are required. Through these wiring-via levels signal and power can be carried throughout the chip and to the chip carrier. The semiconductor industry uses the dual damascene approach to fabricate a wiring- and a via-level simultaneously. However, the dual damascene processing requires more than twenty process steps for one wiring-via level. For an advanced microprocessor with more than ten wiring-via levels the step count for interconnects exceeds that for front end processing. Currently, the dual damascene processing is becoming the most time-consuming step in the processing sequence and affects the throughput of the semiconductor industry essentially. In this work we present a novel approach to fabricate a multi-tier structure for dual damascene processing based on UV nanoimprint lithography (UV-NIL). By using a soft polymer (PDMS) template with multi-tier patterns, a dual damascene structure for one wiring level and one via level can be directly imprinted in a functional dielectric material simultaneously. This UV-NIL based dual damascene processing reduces the total process steps drastically. The possibility of UV-NIL for dual damascene processing and imprintable dielectric materials as interlayer dielectric (ILD) will be discussed.