A Low-Complexity Generalized Memory Addressing Scheme for Continuous-Flow Fast Fourier Transform

In this paper, a control logic-reduced memory addressing scheme with a modified arithmetic processing unit (PE) for memory-based fast Fourier transform (FFT) is presented. The proposed scheme supports the conflict-free memory accessing and continuous-flow (CF) FFT operation. Furthermore, the timing...

Full description

Saved in:
Bibliographic Details
Published in2018 3rd International Conference on Computer and Communication Systems (ICCCS) pp. 492 - 496
Main Authors Long, Syu-Siang, Hong, Meng-Yao, Shiue, Muh- Tian
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2018
Subjects
Complexity theory
Computer architecture
conflict-free
continuous-flow
Delays
fast fourier transform
Generators
Hardware
in-place
Inverters
memory-based
Registers
Online AccessGet full text

Cover

More Information
Summary:In this paper, a control logic-reduced memory addressing scheme with a modified arithmetic processing unit (PE) for memory-based fast Fourier transform (FFT) is presented. The proposed scheme supports the conflict-free memory accessing and continuous-flow (CF) FFT operation. Furthermore, the timing delay is independent of FFT length and the circuit area is minimized in the proposed address generator. A case study of radix-4 256-point CF-FFT is analyzed. The comparison results synthesized with 90nm CMOS technology show that the hardware complexity is significantly reduced. Therefore, the proposed addressing scheme is suitable for high radix algorithm and long FFT length applications.
DOI:10.1109/CCOMS.2018.8463276