Design of CMOS based low noise amplifier at 60 GHz and it's gain variability through body biasing

This paper presents a low power, high gain low noise amplifier (LNA) design using current re-use inductors and complementary MOS structure. Gain variability has been achieved using forward body bias technique applied in the amplifying transistor. Using current re-use inductors at the drain of the co...

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Bibliographic Details
Published in2017 International Conference on Computer Communication and Informatics (ICCCI) pp. 1 - 6
Main Authors Ninan, Becky Mary, Balamurugan, Karthigha
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2017
Subjects
60 GHz
current re-use
forward body biasing
Gain
gain variability
Inductors
LNA design
Noise figure
Receivers
Threshold voltage
Transistors
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Summary:This paper presents a low power, high gain low noise amplifier (LNA) design using current re-use inductors and complementary MOS structure. Gain variability has been achieved using forward body bias technique applied in the amplifying transistor. Using current re-use inductors at the drain of the complementary MOS structure, drain current is shared between PMOS and NMOS. The width of amplifying transistor is chosen to give minimum noise figure and good input matching. The observations show that the gain obtained by the proposed structure is 8.05dB with low noise figure of 2.14dB. The supply voltage used in the LNA design is 1.1V resulting in a power consumption of 2.607mW.
DOI:10.1109/ICCCI.2017.8117757