High Performance Hardware Implementation of SpikeProp Learning: Potential and Tradeoffs

In this paper the design of a dedicated high-performance hardware architecture for the SpikeProp algorithm is described. The proposed architecture performs the two main phases in spiking neural networks (SNNs) processing: recall and learning. The proposed architecture is flexible with respect to the...

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Bibliographic Details
Published in2007 International Conference on Field-Programmable Technology pp. 129 - 136
Main Authors Nuno-Maganda, M.A., Arias-Estrada, M., Torres-Huitzil, C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2007
Subjects
Artificial neural networks
Bandwidth
Biological system modeling
Biology computing
Computer architecture
Concurrent computing
Equations
Error analysis
Hardware
Neurons
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Summary:In this paper the design of a dedicated high-performance hardware architecture for the SpikeProp algorithm is described. The proposed architecture performs the two main phases in spiking neural networks (SNNs) processing: recall and learning. The proposed architecture is flexible with respect to the number of neurons, the data precision to be used and the number of processing elements. Tradeoffs and limitations of a hardware-based learning rule for SNNs are analyzed. Performance statistics, error analysis and hardware resource consumption are provided. The proposed architecture obtains at least a 10X accelerator factor, and similar precision with respect to C-based SW implementation is obtained.
ISBN:1424414717
9781424414710
DOI:10.1109/FPT.2007.4439241