Over one million TPCC with a 45nm 6-core Xeon® CPU

• Published in: 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers pp. 70 - 71,71a
• Main Authors: Kuppuswamy, R., Sawant, S.R., Balasubramanian, S., Kaushik, P., Natarajan, N., Gilbert, J.D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2009
• Subjects: Built-in self-test; Clocks; CMOS technology; Delay; Design for testability; Frequency; Logic; Packaging; Phase locked loops; Timing
• ISBN: 9781424434589; 1424434580
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2009.4977312

This paper describes the 6-core Xeonreg 7400 series processor family, code-name Dunnington, designed for a broad range of highly power efficient servers. The processor consists of three dual-core 45nm Core TM processors and a shared inclusive 16 MB L3 cache (LLC) integrated on a monolithic 503 mm 2 die. The system interface is FSB based with the l/Os incorporated into the center of the die. The core-to-FSB connection is replaced with an on-die low-latency uncore interface. The uncore arbitrates among core, LLC, and external bus requests. The processor has 1.9 B transistors and is implemented in 45nm CMOS using high-kappa metal-gate transistors and nine copper interconnect layers. The maximum thermal design power is 130 W.