Effects of charge confinement and angular strikes in 40 nm dual- and triple-well bulk CMOS SRAMs

Heavy-ion induced upsets are compared in dual-well and triple-well 40 nm CMOS SRAMs. Charge confinement in triple-well structures triggers the single-event upset reversal mechanism for high LET particles. Due to upset reversal, high LET ion-hits incident at off-normal angles show a decrease in SER c...

Full description

Saved in:
Bibliographic Details
Published in2012 IEEE International Reliability Physics Symposium (IRPS) pp. 5B.3.1 - 5B.3.7
Main Authors Chatterjee, I., Bhuva, B. L., Schrimpf, R. D., Narasimham, B., Wang, J. K., Bartz, B., Pitta, E., Buer, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2012
Subjects
CMOS integrated circuits
CMOS technology
Dual well
Ions
MOSFETs
Multi-node Charge Collection
Multiple Bit Upset
Random access memory
Reinforcing Charge Collection
Single Bit Upset
Single Event Effects
Single Event Upset Reversal
Soft Error
Solid modeling
SRAM
Triple well
Online AccessGet full text

Cover

More Information
Summary:Heavy-ion induced upsets are compared in dual-well and triple-well 40 nm CMOS SRAMs. Charge confinement in triple-well structures triggers the single-event upset reversal mechanism for high LET particles. Due to upset reversal, high LET ion-hits incident at off-normal angles show a decrease in SER compared to normally-incident ions for triple-well SRAM cells.
ISBN:145771678X
9781457716782
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2012.6241845