Reliability study in capacitor less 1T-RAM cells on SOI

We have shown that careful optimization of the write conditions is needed in order to achieve the stringent endurance spec of 10 16 cycles for 1T-RAM cells without compromising the sense margin and retention. The degradation seen during cycling of the cells can be attributed to the creation of inter...

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Bibliographic Details
Published in2010 IEEE International SOI Conference (SOI) pp. 1 - 2
Main Authors Aoulaiche, M, Collaert, N, Simoen, E, Mercha, A, De Wachter, B, Bourdelle, K K, Nguyen, B.-Y, Boedt, F, Delprat, D, Jurczak, M, Altimime, L
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2010
Subjects
Charge carrier processes
Degradation
Logic gates
Random access memory
Reliability
Stress
Transient analysis
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Summary:We have shown that careful optimization of the write conditions is needed in order to achieve the stringent endurance spec of 10 16 cycles for 1T-RAM cells without compromising the sense margin and retention. The degradation seen during cycling of the cells can be attributed to the creation of interface states and carrier trapping at either the source ("0") or drain side ("1"). Overall reduction of the biases, especially VD, will have a beneficial effect on the endurance behavior.
ISBN:9781424491308
1424491304
ISSN:1078-621X
2577-2295
DOI:10.1109/SOI.2010.5641377