A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application

An outphasing power amplifier (PA) is designed and implemented in a 32nm digital CMOS process. The PA uses a transformer power combining configuration with reduced losses at backoff power. In the range of 2.2-2.5GHz, this PA gives 25dBm peak CW power with 40% total efficiency (includes all drivers)....

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Bibliographic Details
Published in2010 Proceedings of ESSCIRC pp. 306 - 309
Main Authors Hongtao Xu, Palaskas, Yorgos, Ravi, Ashoke, Soumyanath, Krishnamurthy
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2010
Subjects
CMOS integrated circuits
Driver circuits
Power amplifiers
Radio frequency
System-on-a-chip
Transistors
Wireless LAN
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Summary:An outphasing power amplifier (PA) is designed and implemented in a 32nm digital CMOS process. The PA uses a transformer power combining configuration with reduced losses at backoff power. In the range of 2.2-2.5GHz, this PA gives 25dBm peak CW power with 40% total efficiency (includes all drivers). The class-D PA takes advantage of 32nm switching speed to achieve good linearity performance. The PA delivers 18dBm average power with 18% total efficiency while meeting 64-QAM WLAN requirements, with no need for linearization.
ISBN:9781424466627
1424466628
ISSN:1930-8833
2643-1319
DOI:10.1109/ESSCIRC.2010.5619705