Latch-Based Clocking for Portable Low-Power Audio Applications

Two DSP algorithms for hearing aids have been integrated on silicon in a 0.18 mum CMOS process. Various level-sensitive two-phase clocking schemes have been evaluated in terms of energy efficiency. Actual measurements have confirmed energy savings of 64% over a recently published clock-gated single-...

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Bibliographic Details
Published in2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings pp. 1640 - 1642
Main Authors Buergin, F., Carbognani, F., Kaeslin, H., Felber, N., Fichtner, W.
Format Conference Proceeding
LanguageEnglish
Published 2006
Subjects
Auditory system
Clocks
Frequency
Hearing aids
Microphones
Noise cancellation
Noise reduction
Signal processing
Signal processing algorithms
Silicon
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Summary:Two DSP algorithms for hearing aids have been integrated on silicon in a 0.18 mum CMOS process. Various level-sensitive two-phase clocking schemes have been evaluated in terms of energy efficiency. Actual measurements have confirmed energy savings of 64% over a recently published clock-gated single-edge-triggered one-phase implementation. Most of these improvements can be attributed to the thinning out of the clock tree made possible by the relaxed slew and skew constraints of level-sensitive clocking schemes
ISBN:9781424401604
1424401607
DOI:10.1109/ICSICT.2006.306358