A CAD tool for design and analysis of CNFET circuits

• Published in: 2010 IEEE International Conference of Electron Devices and Solid-State Circuits pp. 1 - 4
• Main Authors: Jiale Huang, Minhao Zhu, Gupta, Pallav, Shengqi Yang, Rubin, Steven M, Garret, Gilda, Jin He
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2010
• Subjects: Adders; CNTFETs; Design automation; Hardware design languages; Layout; Libraries; Logic gates
• ISBN: 9781424499977; 1424499976
• DOI: 10.1109/EDSSC.2010.5713735

In this paper, we present a graphical computer-aided design (CAD) environment for the design, analysis, and layout of carbon nanotube (CNT) field-effect transistor (CNFET) circuits. This work is motivated by the fact that such a tool currently does not exist in the public domain for researchers. Our tool has been integrated within Electric - a very powerful, yet free CAD system for custom design of integrated circuits (ICs). The tool supports CNFET schematic and layout entry, rule checking, and HSpice/VerilogA netlist generation. We provide users with a customizable CNFET technology library with the ability to specify λ-based design rules. We showcase the capabilities of our tool by demonstrating the design of a CNFET standard cell library and a 16-bit carry-select adder. We hope that the availability of this tool will invigorate the CAD community to explore novel ideas in CNFET circuit design.