A VLSI structural optimization method and workflow based on synthesis frequency inflexion

A synthesis frequency inflexion phenomenon of VLSI synthesis process is discussed, and then a VLSI structural optimization method with its workflow based on the analysis of synthesis frequency infrexion and register insertion is proposed. Registers are usually used for sequential synchronization and...

Full description

Saved in:
Bibliographic Details
Published in2008 9th International Conference on Solid-State and Integrated-Circuit Technology pp. 1897 - 1900
Main Authors Chungan Peng, Ying Li, Xiaoxin Cui, Xixin Cao, Dunshan Yu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2008
Subjects
Circuit synthesis
Clocks
Design optimization
Digital integrated circuits
Frequency synthesizers
Hardware
Integrated circuit synthesis
Optimization methods
Registers
Very large scale integration
Online AccessGet full text

Cover

More Information
Summary:A synthesis frequency inflexion phenomenon of VLSI synthesis process is discussed, and then a VLSI structural optimization method with its workflow based on the analysis of synthesis frequency infrexion and register insertion is proposed. Registers are usually used for sequential synchronization and increasing maximum operating frequency, but in this issue, they are utilized to avoid excessively high combinational logic expenditure. In the H.264 macroblock-level SAD tree case, 50.6% improvement in speed is achieved at the expense of 2.9% increment in area. This method contains no complex algorithm, but exhibits good operability and generality. It is very suitable and useful for complicated VLSI structural design and/or their critical path optimization.
ISBN:9781424421855
1424421853
DOI:10.1109/ICSICT.2008.4734930