Drain Extended NMOS High Current Behavior and ESD Protection Strategy for HV Applications in Sub-100nm CMOS Technologies

In this work the high current behavior of drain-extended nMOS transistors (DEnMOS) built in a state-of-the-art 65nm CMOS technology were investigated. It shown that a sufficient level of ESD robustness (I T2 ~2mA/mum) can be achieved through substrate biasing. The concept will be exploited to build...

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Bibliographic Details
Published in2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual pp. 342 - 347
Main Authors Boselli, G., Vassilev, V., Duvvury, C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2007
Subjects
CMOS technology
DEnMOS
Diodes
Electrostatic discharge
ESD
Implants
MOS devices
MOSFETs
Protection
Robustness
state-of-art CMOS technology
Thyristors
USB2.0
Voltage
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Summary:In this work the high current behavior of drain-extended nMOS transistors (DEnMOS) built in a state-of-the-art 65nm CMOS technology were investigated. It shown that a sufficient level of ESD robustness (I T2 ~2mA/mum) can be achieved through substrate biasing. The concept will be exploited to build robust ESD protections
ISBN:9781424409181
1424409187
ISSN:1541-7026
1938-1891
DOI:10.1109/RELPHY.2007.369913