A background calibration technology for capacitance mismatch in pipelined ADCs with 2.5-bit/stage MDAC

• Published in: 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) pp. 924 - 926
• Main Authors: Hai-bin Li, Rui Li, Bing-Yan Hu, Tao Jiang, Yu-Chun Chang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2016
• Subjects: Calibration; Capacitance; Capacitors; Clocks; CMOS process; Field programmable gate arrays; Signal to noise ratio
• ISBN: 1467397172; 9781467397179
• DOI: 10.1109/ICSICT.2016.7999081

In traditional pipelined ADCs, errors originated by capacitance mismatch, finite amplifier gain, incomplete settling and offset. To overcome capacitance mismatch for >=2.5-bit/stage MDAC architecture, a new background digital calibration strategy is proposed in this paper. Based on this technique, a 14-bit, 40MS/s pipelined ADC is implemented. The simulation results show that ENOB is improved from 9.7 bits to 13.3 bits with σ=0.5% capacitance mismatch within 1s. The chip is fabricated in 0.18um CMOS process, occupied an active area of 4×4mm2, including on-chip decouple capacitors, with 110mW power consumption at 3.3 V.