Design and Implementation of a 1.5Gsps Digital Channelized Receiver

Based on the derivation of the efficient implementation structure of the frequency domain polyphase filter digital channelized receiver, a digital channelized receiver was achieved on the hardware platform with I/Q sampling, 1500Msps, 64channels. In order to ensure good performance of the system, op...

Full description

Saved in:
Bibliographic Details
Published in2010 2nd International Conference on Information Engineering and Computer Science pp. 1 - 4
Main Authors Xu, Shichao, Liu, Guoman, Gao, Meiguo, Qin, Guo Jie
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2010
Subjects
Clocks
Data processing
Field programmable gate arrays
Frequency domain analysis
Hardware
Low pass filters
Receivers
Online AccessGet full text

Cover

More Information
Summary:Based on the derivation of the efficient implementation structure of the frequency domain polyphase filter digital channelized receiver, a digital channelized receiver was achieved on the hardware platform with I/Q sampling, 1500Msps, 64channels. In order to ensure good performance of the system, optimization of the processor speed and processor resources was fully considered during the design process of the whole system. The actual ultra-wideband signal test results show that the digital channelized receiver is in good performance.
ISBN:1424479398
9781424479399
ISSN:2156-7379
DOI:10.1109/ICIECS.2010.5677721