Scalable serial-parallel multiplier over GF(2m) by hierarchical pre-reduction and input decomposition

• Published in: 2009 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 2910 - 2913
• Main Authors: Meher, P.K., Lee, C.-Y.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2009
• Subjects: Bandwidth; Clocks; Elliptic curve cryptography; elliptic curve cryptography (ECC); Error correction; Feeds; Finite field; finite field multiplication; Galois field; Galois fields; Polynomials; Scalability; Throughput; Very large scale integration; very large scale integration (VLSI)
• ISBN: 1424438276; 9781424438273
• ISSN: 0271-4302
• DOI: 10.1109/ISCAS.2009.5118411

This paper presents a novel serial-parallel architecture for finite field multiplications over GF(2 m ) defined by irreducible trinomials as field polynomials. By recursive decomposition of one of the operands, and hierarchical pre-reduction of the other, it is possible to feed multiple bits in parallel to the serial-parallel structure. The level of parallelism could be doubled after each level of decomposition of the input operand, when high throughput rate is required. One of the key features of the proposed design is that its clock-period remains invariant with the digit-size. The area-complexity of the proposed design increases linearly with the digit-size, which is unlike some of the existing architectures, where area-complexity increases quadratically with the digit-size. Although the proposed structure involves more area compared with some of the existing architectures, since the clock-period of the proposed design is small, it involves significantly less area-delay complexity than the others.