Device-level PBTI-induced timing jitter increase in circuit-speed random logic operation

• Published in: Digest of technical papers - Symposium on VLSI Technology pp. 1 - 2
• Main Authors: Lu, J. W., Vaz, C., Campbell, J. P., Ryan, J. T., Cheung, K. P., Jiao, G. F., Bersuker, G., Young, C. D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2014
• Subjects: Degradation; Logic gates; Stress; Stress measurement; Time measurement; Timing jitter
• ISBN: 9781479933310; 1479933317
• ISSN: 0743-1562
• DOI: 10.1109/VLSIT.2014.6894387

We utilize eye-diagram measurements of timing jitter to investigate the impact of PBTI in devices subject to DC as well as ring oscillator (RO) and pseudo-random binary sequence (PRBS) stress waveforms. We observe that RO measurements miss the relevant random timing jitter increases which are well captured using PRBS measurements. We also observe that DC, RO, and PRBS stresses all introduce similar increases in random timing jitter. This calls into question the widely assumed degradation headroom between DC and AC measurements. This work collectively provides a snapshot of PBTI degradation in "real" circuit environments. It provides a path for more accurate and realistic circuit lifetime estimations and circuit timing budget criteria.