A partition level floorplan method based on data flow analysis for physical design of digital IC

This paper presents a partition level floorplan method for physical design of digital integrated circuit, which based on data flow analysis. It uses Cadence company P&R tool innovus to make floorplan, and takes a X86 CPU's south bridge design for example to introduce how to use this method...

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Published in2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM) pp. 74 - 77
Main Authors Yinan Zhang, Xiaohong Peng
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2017
Subjects
Bridges
Browsers
Clocks
data flow
floorplan
Physical design
Pins
Timing
timing closure
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ISBN9781538635056
1538635054
DOI10.1109/ICAM.2017.8242141

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Abstract This paper presents a partition level floorplan method for physical design of digital integrated circuit, which based on data flow analysis. It uses Cadence company P&R tool innovus to make floorplan, and takes a X86 CPU's south bridge design for example to introduce how to use this method to guide floorplan in detail. This method is more effective to improve the quality of floorplan for advanced process technology and high speed IC design.
AbstractList This paper presents a partition level floorplan method for physical design of digital integrated circuit, which based on data flow analysis. It uses Cadence company P&R tool innovus to make floorplan, and takes a X86 CPU's south bridge design for example to introduce how to use this method to guide floorplan in detail. This method is more effective to improve the quality of floorplan for advanced process technology and high speed IC design.
Author Xiaohong Peng
Yinan Zhang
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  surname: Xiaohong Peng
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  organization: VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China
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Snippet This paper presents a partition level floorplan method for physical design of digital integrated circuit, which based on data flow analysis. It uses Cadence...
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SubjectTerms Bridges
Browsers
Clocks
data flow
floorplan
Physical design
Pins
Timing
timing closure
Title A partition level floorplan method based on data flow analysis for physical design of digital IC
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