A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator
A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion lineari...
Saved in:
| Published in | 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) pp. 225 - 228 |
|---|---|
| Main Authors | , , , , |
| Format | Conference Proceeding |
| Language | English |
| Published |
IEEE
01.11.2017
|
| Subjects | |
| Online Access | Get full text |
Cover
Loading…
| Abstract | A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the decoupling capacitor. The achieved peak SNDR, SFDR, and FoM are 64.2 dB, 80.5 dBc, and 107.3 fJ/conversion-step, respectively. |
|---|---|
| AbstractList | A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the decoupling capacitor. The achieved peak SNDR, SFDR, and FoM are 64.2 dB, 80.5 dBc, and 107.3 fJ/conversion-step, respectively. |
| Author | Hongyu Li Zhihua Wang Jia Liu Weitao Li Fule Li |
| Author_xml | – sequence: 1 surname: Weitao Li fullname: Weitao Li organization: Inst. of Microelectron., Tsinghua Univ., Beijing, China – sequence: 2 surname: Fule Li fullname: Fule Li email: lifule@tsinghua.edu.cn organization: Inst. of Microelectron., Tsinghua Univ., Beijing, China – sequence: 3 surname: Jia Liu fullname: Jia Liu organization: Inst. of Microelectron., Tsinghua Univ., Beijing, China – sequence: 4 surname: Hongyu Li fullname: Hongyu Li organization: Inst. of Microelectron., Tsinghua Univ., Beijing, China – sequence: 5 surname: Zhihua Wang fullname: Zhihua Wang organization: Inst. of Microelectron., Tsinghua Univ., Beijing, China |
| BookMark | eNotz71OwzAUQGEjwQClLwCLX8Cpr-3YzhiFX6kIRLpX165dLCVOlARVfXsGOp3tk84duc5DDoQ8AC8AeLWp27ZpCsHBFFYoLkpzRdaVsVBKqyUYK27JV01BMpcWCpp_tJuZjmkMXcrhQOdfN2E-pnxkbf1N66eGntLyQ7vhxIYY57DQwzljnzz1Qz_ihMsw3ZObiN0c1peuyO7lede8se3n63tTb1mq-MKMEq4EiwakklAGHYX3zmnvvC9tqAS3WskoDSJGY41TQWkujETpKo8gV-Txn00hhP04pR6n8_6yKf8Ako5KVw |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IL CBEJK RIE RIL |
| DOI | 10.1109/ASSCC.2017.8240257 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library Online IEEE Proceedings Order Plans (POP All) 1998-Present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library Online url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| EISBN | 9781538631782 1538631784 |
| EndPage | 228 |
| ExternalDocumentID | 8240257 |
| Genre | orig-research |
| GroupedDBID | 6IE 6IL CBEJK RIE RIL |
| ID | FETCH-LOGICAL-i90t-742b518a7134315e6f2ccbb6cbcc58e9208643f37aaaf787b4e460273a3b9ca13 |
| IEDL.DBID | RIE |
| IngestDate | Thu Jun 29 18:37:42 EDT 2023 |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-i90t-742b518a7134315e6f2ccbb6cbcc58e9208643f37aaaf787b4e460273a3b9ca13 |
| PageCount | 4 |
| ParticipantIDs | ieee_primary_8240257 |
| PublicationCentury | 2000 |
| PublicationDate | 2017-Nov. |
| PublicationDateYYYYMMDD | 2017-11-01 |
| PublicationDate_xml | – month: 11 year: 2017 text: 2017-Nov. |
| PublicationDecade | 2010 |
| PublicationTitle | 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
| PublicationTitleAbbrev | ASSCC |
| PublicationYear | 2017 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| Score | 1.7102761 |
| Snippet | A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 225 |
| SubjectTerms | analog-to-digital converter Calibration Capacitors Clocks CMOS integrated circuits CMOS technology Conferences dynamic comparator Generators hybrid ADC pipelined subranging-SAR ADC reference voltage buffer Solid state circuits |
| Title | A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator |
| URI | https://ieeexplore.ieee.org/document/8240257 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3PS8MwGA3bTp5UNvE3OXg0XdOmWXMs1TGEybATdhtJ-kWGso6tRfCvN2k7RfHgLYRAQkLyeF--9z6EbqSfs0ALRYzFM8IsRBElISYWTgQ1VNt32RHF6SOfPLOHRbTooNsvLQwA1Mln4Llm_ZefF7pyobJh7L4ColEXdUdCNFqtvQ7GF8Mky9LUJWuNvHbgj4opNWCMD9F0P1WTJ_LqVaXy9McvF8b_ruUIDb6leXj2BTrHqAPrPpolmIaW45aYcn-aDXd4s9o4oTnkeFdZPuxMB19Iljzh5C7FLvaK34p3UhizgxLnTVV6rFsn8GI7QPPx_TydkLZUAlkJvySW36qIxtIJQ0MaATeB1kpxrbSOYhCBJS4sNOFISmnsFVUMGHdONjJUQksanqDeuljDKcKRkpFWeRyD0kxSLn3DgUnGY2oUDfwz1Hebsdw0ZhjLdh_O_-6-QAfuQBrx3iXqldsKriyKl-q6Pr5Pkhmd3A |
| link.rule.ids | 310,311,783,787,792,793,799,27937,55086 |
| linkProvider | IEEE |
| linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3PS8MwFA5zHvSksom_zcGj6Zo1zdJjqY6p6xh2wm4jSRMZyjq2FsG_3qTtJooHbyEEEl5IvryX930PgBvupqQrA4G0wTNEDEQhwRVDBk4CrLE097J1FOMRHbyQx6k_bYDbLRdGKVUmnynHNsu__DSThQ2VdZj9CvB7O2DXvKsZrdhaGyaMG3TCJIkim67Vc-qhP2qmlJDRPwDxZrIqU-TNKXLhyM9fOoz_Xc0haH-T8-B4CztHoKEWLTAOIfaMl5tDTN046azhcr60VHOVwnVhPGIrO_iKkvAZhncRtNFX-J59oEzrtcphWtWlh7LWAs9WbTDp30-iAaqLJaB54ObIeLjCx4xbaqiHfUV1V0ohqBRS-kwFXWMv4mmvxznX5pAKogi1WjbcE4Hk2DsGzUW2UCcA-oL7UqSMKSEJx5S7mirCCWVYC9x1T0HLGmO2rOQwZrUdzv7uvgZ7g0k8nA0fRk_nYN9uTkXluwDNfFWoS4Ppubgqt_ILBAShJw |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2017+IEEE+Asian+Solid-State+Circuits+Conference+%28A-SSCC%29&rft.atitle=A+13-bit+160MS%2Fs+pipelined+subranging-SAR+ADC+with+low-offset+dynamic+comparator&rft.au=Weitao+Li&rft.au=Fule+Li&rft.au=Jia+Liu&rft.au=Hongyu+Li&rft.date=2017-11-01&rft.pub=IEEE&rft.spage=225&rft.epage=228&rft_id=info:doi/10.1109%2FASSCC.2017.8240257&rft.externalDocID=8240257 |