A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator

A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion lineari...

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Bibliographic Details
Published in2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) pp. 225 - 228
Main Authors Weitao Li, Fule Li, Jia Liu, Hongyu Li, Zhihua Wang
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2017
Subjects
analog-to-digital converter
Calibration
Capacitors
Clocks
CMOS integrated circuits
CMOS technology
Conferences
dynamic comparator
Generators
hybrid ADC
pipelined subranging-SAR ADC
reference voltage buffer
Solid state circuits
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Summary:A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the decoupling capacitor. The achieved peak SNDR, SFDR, and FoM are 64.2 dB, 80.5 dBc, and 107.3 fJ/conversion-step, respectively.
DOI:10.1109/ASSCC.2017.8240257