A test solution for oxide thickness variations in the ATMEL TSTAC™ eFlash technology

• Published in: 2011 6th International Conference on Design and Technology of Integrated Systems in Nanoscale Era pp. 1 - 6
• Main Authors: Mauroux, P.-D, Virazel, A., Bosio, A., Dilillo, L., Girard, P., Pravossoudovitch, S., Godard, B., Festes, G., Vachez, L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2011
• Subjects: Arrays; characterization and test; Electric fields; embedded Flash; NAND array; Nonvolatile memory; oxide thickness; Programming; Reliability; retention; SPICE; Transistors
• ISBN: 9781612848990; 1612848990
• DOI: 10.1109/DTIS.2011.5941431

The embedded Flash (eFlash) technologies are based on the Floating Gate (FG) concept and can be subject to defects leading to retention and reliability problems. One of the most important aspects to guarantee high retention and reliability levels is the oxide thickness where the electric field is applied for charge injection and removal. In this paper, we analyze the impact of a defective oxide thickness on memory core cells built with the ATMEL TSTAC™ technology. We show how this variation of oxide thickness impacts the erase and write operations and consequently, the retention and the reliability of the memory. Then, we propose a test solution able to characterize and test the oxide thickness. This solution consists in adapting the inhibition voltage of non-selected bit lines during write operations.