Defect and fault detection in combinational circuits: Techniques and analysis

The integration level in today's word is continuously increasing in VLSI chips. So that complexity of testing is a major challenge. That is because the internal chip modules have become increasingly midcult to access. There is a significant amount of the testing cost as compared to the total ma...

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Bibliographic Details
Published in2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI) pp. 332 - 337
Main Authors Arya, Namita, Singh, Amit Prakash
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2017
Subjects
Adders
Electrical fault detection
Fault detection
Light emitting diodes
Redundancy
Testing
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Summary:The integration level in today's word is continuously increasing in VLSI chips. So that complexity of testing is a major challenge. That is because the internal chip modules have become increasingly midcult to access. There is a significant amount of the testing cost as compared to the total manufacturing cost. Hence there is a necessity to reduce the testing cost. The main factor is the time required to test the circuitry that has the biggest impact on testing cost of a chip. This time can be decreased by reducing the number of tests required to test the chip. So, we simply need to devise a test set that should be small in size. There is one way to generate a small test set is to compact a large test set parameters. The main drawback of the compaction results on the quality of the original test set. This aspect of compaction has motivated the work presented here with some methods of fault detection and avoidance techniques to test the circuit for a fault-free environment.
DOI:10.1109/ICACCI.2017.8125862