A 288-μW 6-GHz hybrid dynamic comparator with 54-ps delay in 40-nm CMOS

This paper presents an energy-efficient high-speed hybrid dynamic comparator with reduced delay in 40-nm CMOS process. The first dynamic amplifying stage uses PMOS input to reduce the common-mode voltage, thus the required minimum supply voltage, while enhancing the positive feedback to reduce the d...

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Bibliographic Details
Published in2016 IEEE MTT-S International Wireless Symposium (IWS) pp. 1 - 4
Main Authors Sen Huang, Lin He, Yu-Kai Chou, Fujiang Lin
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2016
Subjects
Clocks
CMOS
Delays
dynamic comparator
Energy efficiency
energy efficient
high speed
hybrid comparator
Latches
low power
Threshold voltage
Transconductance
Transistors
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Summary:This paper presents an energy-efficient high-speed hybrid dynamic comparator with reduced delay in 40-nm CMOS process. The first dynamic amplifying stage uses PMOS input to reduce the common-mode voltage, thus the required minimum supply voltage, while enhancing the positive feedback to reduce the discharge time in a low-power manner. The second quasi-dynamic latching stage uses NMOS input to gain the transconductance, thus reducing the latch delay with negligible static power, while needing no additional clock signal. Simulation results show that the proposed comparator operates up to 6 GHz with 54-ps delay, while consuming only 288 μW at 1.1-V supply.
DOI:10.1109/IEEE-IWS.2016.7585447