A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS

This paper demonstrates a IV 200MS/s pipelined ADC with digital background calibration in 65nm digital CMOS process.

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Bibliographic Details
Published in2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers pp. 546 - 634
Main Authors Hsueh, Kang-Wei, Chou, Yu-Kai, Tu, Yu-Hsuan, Chen, Yi-Fu, Yang, Ya-Lun, Li, Hung-Sung
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.02.2008
Subjects
Calibration
Capacitors
CMOS process
Convergence
Costs
Fluctuations
Semiconductor device measurement
Signal processing
Silicon
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Summary:This paper demonstrates a IV 200MS/s pipelined ADC with digital background calibration in 65nm digital CMOS process.
ISBN:1424420105
9781424420100
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2008.4523299