A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET

• Published in: Digest of technical papers - IEEE International Solid-State Circuits Conference Vol. 65; pp. 116 - 118
• Main Authors: Guo, Z., Mostafa, A., Elshazly, A., Chen, B., Wang, B., Han, C., Wang, C., Zhou, D., Visani, D., Hsiao, E., Chu, F., Lu, F., Cui, G., Zhang, H., Wang, H., Zhao, H., Lin, J., Gu, J., Luo, L., Jiang, L., Singh, M., Gambhir, M., Hasan, M., Wu, M., Yoo, M. J., Liu, P., Kollu, S., Ye, T., Zhao, X., Yang, X., Han, X., Huang, Y., Sun, Y., Yu, Z., Jiang, Z. H., Adal, Z., Yan, Z.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 20.02.2022
• Subjects: Bandwidth; Conferences; Data centers; FinFETs; Insertion loss; Next generation networking; Transceivers
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC42614.2022.9731650

With increasing demand in next-generation data centers and high-performance computing and networking, wireline transceivers are required to operate at 112Gb/s to provide high bandwidth [1]-[3], meanwhile it is necessary to handle >40dB insertion loss to support legacy channels and large package designs [4]. Low-power design is also critical for the integration of multiple transceivers [5]. To advance state-of-the-art design, this work presents an ADC/DAC-DSP based PAM-4 transceiver capable of equalizing >50dB lossy channels and achieving 112.5Gb/s per channel in a 5nm FinFET process with a power efficiency of 4.5pJ/b.