Analysis of array biasing in crosspoint memories for leakage power minimization

• Published in: 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) pp. 17 - 20
• Main Authors: Belay, Yilkal A., Cabrini, A., Torelli, G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2017
• Subjects: Memory management; Microprocessors; Power demand; Resistance; Switches; Threshold voltage
• DOI: 10.1109/PRIME.2017.7974096

Thanks to the recent development of resistance-switching memories, crosspoint array has become an attractive architecture to obtain high-density storage. However, crosspoint arrays suffer from sneak current paths and voltage drops on interconnection lines, which may lead to various challenges such as excessive leakage power, write failure, write disturbance, and insufficient read margin. In this paper we focus our attention on leakage power consumption. We demonstrate that the bias scheme that minimizes leakage power consumption is generally a function of array size and selector nonlinearity. By considering a generic x bias scheme (where selected and unselected wordlines and unselected and selected bitlines are biased to voltages V W , x · V W , (1 - x) · V W , and ground, respectively) and by employing a mathematical model to accurately estimate the leakage power, we study how the bias scheme can be designed for minimum leakage power consumption for a wide range of array sizes and selector nonlinearities. We demonstrate that the value of factor x that gives minimum power consumption lies somewhere between 1/3 and 1/2.