Clock generation for a 32nm server processor with scalable cores

Within a given power envelope, the performance of a multi-core enterprise processor is greatly affected by inter-core (including I/O) data throughput and data transport latency. This paper presents the implementation of a clock system targeting low-power low-skew high-data throughput and low latency...

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Bibliographic Details
Published in2011 IEEE International Solid-State Circuits Conference pp. 82 - 83
Main Authors Shenggao Li, Krishnakumar, A, Helder, E, Nicholson, R, Jia, V
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.02.2011
Subjects
Clocks
Inductors
Jitter
Metals
Phase locked loops
Program processors
Synchronization
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Summary:Within a given power envelope, the performance of a multi-core enterprise processor is greatly affected by inter-core (including I/O) data throughput and data transport latency. This paper presents the implementation of a clock system targeting low-power low-skew high-data throughput and low latency for a next-generation Xeon ® server processor with scalable cores in a 32nm 9-metal digital CMOS process.
ISBN:9781612843032
1612843034
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2011.5746229