Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network
This paper proposes an efficient method to find the worst case of voltage violation by multi-domain clock gating in an on-chip power network. We first present a voltage response in an arbitrary multi-domain clock gating pattern, using a superposition technique. Then, an integer linear programming (I...
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Published in | 2008 Design, Automation and Test in Europe pp. 537 - 540 |
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Main Authors | , , , , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.03.2008
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Subjects | |
Online Access | Get full text |
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Summary: | This paper proposes an efficient method to find the worst case of voltage violation by multi-domain clock gating in an on-chip power network. We first present a voltage response in an arbitrary multi-domain clock gating pattern, using a superposition technique. Then, an integer linear programming (ILP) formulation is proposed to identify the worst-case gating pattern and the maximum variation area. The ILP based method is significantly faster than a conventional method based on enumeration. The experimental results are also compared with a case where peak voltage variation is induced, which shows the latter technique largely underestimated the overall variation effect. |
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ISBN: | 3981080130 9783981080131 |
ISSN: | 1530-1591 1558-1101 |
DOI: | 10.1109/DATE.2008.4484906 |