Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network

This paper proposes an efficient method to find the worst case of voltage violation by multi-domain clock gating in an on-chip power network. We first present a voltage response in an arbitrary multi-domain clock gating pattern, using a superposition technique. Then, an integer linear programming (I...

Full description

Saved in:
Bibliographic Details
Published in2008 Design, Automation and Test in Europe pp. 537 - 540
Main Authors Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Murgai, R., Shibuya, T., Ito, N., Chung-Kuan Cheng
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2008
Subjects
Circuits
Clocks
Helium
Integer linear programming
Laboratories
Logic
Network-on-a-chip
Packaging
Very large scale integration
Voltage
Online AccessGet full text

Cover

More Information
Summary:This paper proposes an efficient method to find the worst case of voltage violation by multi-domain clock gating in an on-chip power network. We first present a voltage response in an arbitrary multi-domain clock gating pattern, using a superposition technique. Then, an integer linear programming (ILP) formulation is proposed to identify the worst-case gating pattern and the maximum variation area. The ILP based method is significantly faster than a conventional method based on enumeration. The experimental results are also compared with a case where peak voltage variation is induced, which shows the latter technique largely underestimated the overall variation effect.
ISBN:3981080130
9783981080131
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2008.4484906