A 40Gb/s TX and RX chip set in 65nm CMOS

• Published in: 2011 IEEE International Solid-State Circuits Conference pp. 146 - 148
• Main Authors: Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2011
• Subjects: Clocks; CMOS integrated circuits; Delay; Finite impulse response filter; Generators; Phase locked loops; Transceivers

Next generation optical and electrical communications such as chip-to-chip serial links or 100GbE require very-high-speed transceivers. At tens of Gb/s, both transmitters and receivers suffer from inadequate bandwidth and high power consumption. One major difficulty arises from the performance degra...