A 40Gb/s TX and RX chip set in 65nm CMOS

Next generation optical and electrical communications such as chip-to-chip serial links or 100GbE require very-high-speed transceivers. At tens of Gb/s, both transmitters and receivers suffer from inadequate bandwidth and high power consumption. One major difficulty arises from the performance degra...

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Bibliographic Details
Published in2011 IEEE International Solid-State Circuits Conference pp. 146 - 148
Main Authors Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.02.2011
Subjects
Clocks
CMOS integrated circuits
Delay
Finite impulse response filter
Generators
Phase locked loops
Transceivers
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Summary:Next generation optical and electrical communications such as chip-to-chip serial links or 100GbE require very-high-speed transceivers. At tens of Gb/s, both transmitters and receivers suffer from inadequate bandwidth and high power consumption. One major difficulty arises from the performance degradation of FIR-based FFEs as the FF's CK-Q delay becomes significant to one bit period. Using passive components as delay elements can relax this issue to some extent, but the untunable delay is quite vulnerable to PVT variations. Traditional DFEs also suffer from speed limitation in its feedback loop, and parallelization schemes usually introduce complex circuits and high power consumption. This paper presents a full-rate 40Gb/s transceiver prototype significantly alleviating the above issues.
ISBN:9781612843032
1612843034
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2011.5746257