Smallest Bit-Line Contact of 76nm pitch on NAND Flash Cell by using Reversal PR (Photo Resist) and SADP (Self-Align Double Patterning) Process

For the scaling down of design rule to develop the high density NAND flash device, the reduced active area forces to form a small bit-line contact with the low contact-resistance, as well as the low junction leakage current due to the borderless contact. In this paper, we propose a novel process to...

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Bibliographic Details
Published in2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference pp. 356 - 358
Main Authors Byungjoon Hwang, Jaehwang Shim, Jang-Ho Park, Kwangseok Lee, Sunghyun Kwon, Sang-Yong Park, Yoonmoon Park, Dong-Hwa Kwak, Jaekwan Park, Won-Seong Lee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2007
Subjects
Atomic layer deposition
Contact resistance
Electronic mail
Etching
Fabrication
Leakage current
Lithography
Production
Research and development
Resists
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Summary:For the scaling down of design rule to develop the high density NAND flash device, the reduced active area forces to form a small bit-line contact with the low contact-resistance, as well as the low junction leakage current due to the borderless contact. In this paper, we propose a novel process to make 38 nm small size contact with 76 nm pitch by using the reversal PR (photo resist) and SADP (self-align double patterning) process. The methods to minimize the contact resistance and to suppress the junction leakage current were explained on NAND flash device with 38 nm node technology.
ISBN:9781424406524
1424406528
ISSN:1078-8743
2376-6697
DOI:10.1109/ASMC.2007.375063