Design of hybrid memristor-MOS XOR and XNOR logic gates

Two hybrid memristor-MOS exclusive OR (XOR) and exclusive NOR (XNOR) logic gates based on Memristor Ratioed Logic (MRL) are presented. The proposed gates present logic states with voltages, and implement the logic operation within one clock cycle. The designs ease the voltage degradation problem of...

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Bibliographic Details
Published in2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) pp. 1 - 2
Main Authors Xiaoyan Xu, Xiaole Cui, Mengying Luo, Qiujun Lin, Yichi Luo, Yufeng Zhou
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2017
Subjects
Degradation
Delays
Integrated circuit modeling
Logic gates
memristor
Memristors
MOSFET
MRL
XNOR gate
XOR gate
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Summary:Two hybrid memristor-MOS exclusive OR (XOR) and exclusive NOR (XNOR) logic gates based on Memristor Ratioed Logic (MRL) are presented. The proposed gates present logic states with voltages, and implement the logic operation within one clock cycle. The designs ease the voltage degradation problem of the original MRL logic gates, while consuming fewer area overhead and less delay than their counterparts.
DOI:10.1109/EDSSC.2017.8126414