Gate Disturb Reduction in a Silicon Nanocrystal Flash EEPROM by Means of Natural Threshold Voltage Reduction

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Bibliographic Details
Published in	2006 21st IEEE Non-Volatile Semiconductor Memory Workshop pp. 56 - 57
Main Authors	Swift, C.T., Hoefler, A., Kirichenko, T., Muralidhar, R., Prinz, E., Rajesh Rao, Rinkenberger, G., Sadd, M., Steimle, R.
Format	Conference Proceeding
Language	English
Published	IEEE 2006
Subjects	CMOS technology Doping profiles EPROM Indium Nanocrystals Nonvolatile memory Silicon Substrates Tellurium Threshold voltage
Online Access	Get full text

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